Secure Triple Track Logic Robustness Against Differential Power and Electromagnetic Analyses

In the last century, modern cryptology has mainly focused on defining cryptosystems resistant against logical attacks. But lately, with the increasing use of secure embedded systems, researchers focused on the correlation between data processed by cryptographic devices and their physical leakages. As a result, new, efficient side-channel attacks exploiting these physical leakages have appeared such as Differential Power Analysis (DPA) [1] and Differential Electromagnetic Analysis (DEMA) [2]. Several countermeasures against power analysis have been proposed in former works [3-5, 6-8]. Most of these aim at hiding or masking the correlation between processed data and physical leakages, by adding, for example, random power consumption. In this context, self-timed circuits seem an interesting alternative, since it is more difficult to correlate the leaking syndromes to the data flowing in a secure design in the absence of a global synchronization signal [5, 9]. Among all available asynchronous circuit families, QDI (Quasi-Delay Insensitive) circuits offer another main advantage, namely the return to zero dual rail encoding used to encode logic values [10, 11]. The protocol of this logic consists of two phases: precharge and evaluation. The precharge phase allows starting a computation from a known electrical state, for example 00. The evaluation phase consists in a transition of exactly one wire such as from encoding 00 to encoding 10 or from 00 to 01. The differential power signature of QDI circuits may therefore be strongly reduced, provided the use of perfectly balanced cells. Several implementations of robust dual rail cells are available in the literature [6-8, 11-13]. Most of these have been proposed to design robust ASIC, and a few works were dedicated to mapping of secure dual rail logic on FPGA [14]. Among all these works, an investigation of the effective robustness against DPA of dual rail logic has been introduced in [15, 16, 17-23]. Tiri and Verbauwhede [15] proposed a new design flow to implement circuits resistant against DPA. Kulikowski et al. [16] presented a general method and case studies to support their proposal of a directional discharge protocol, which ensures that dual rail circuits are always fully discharged and charged in each cycle. Tiri et al. [17] were the first to propose the use of dual rail logic with precharge (DPL). They also proposed [19] the wave dynamic differential logic style (WDDL) that uses a ABSTRACT1